Circuit for protecting chips against IDD fluctuation attacks

ABSTRACT

A method of providing for resistance to attack by monitoring of an integrated circuit by means of monitoring I dd  current changes. The method comprises the step of including a spurious noise generation circuit as part of the integrated circuit, to increase the Signal to Noise Ratio in the I dd  signal and obscure meaningful information.

CROSS REFERENCES TO RELATED APPLICATIONS

The following co-pending U.S. patent applications, identified by theirU.S. patent application serial numbers. (USSN) and Docket numbers (inbrackets), were filed simultaneously to the present application on Jul.10, 1998, and are hereby incorporated by cross-reference:

09/113,060 09/113,070 09/113,073 09/112,748 (ART04) (ART01) (ART02)(ART03) 09/112,747 09/112,776 09/112,750 09/112,746 (ART09) (ART06)(ART07) (ART08) 09/112,743 09/112,742 09/112,741 09/112,740 (ART13)(ART10) (ART11) (ART12) 09/112,739 09/113,053 09/112,738 09/113,067(ART18) (ARTI5) (ART16) (ART17) 09/113,063 09/113,069 09/112,74409/113,058 (ART22) (ART19) (ART20) (ART21) 09/112,777 09/113,22409/112,804 09/112,805 (ART27) (ART24) (ART25) (ART26) 09/113,07209/112,785 09/112,797 09/112,796 (ART31) (ART28) (ART29) (ART30)09/113,071 09/112,824 09/113,090 09/112,823 (ART38) (ART32) (ART33)(ART34) 09/113,222 09/112,786 09/113,051 09/112,782 (ART44) (ART39)(ART42) (ART43) 09/113,056 09/113,059 09/113,091 09/112,753 (ART48)(ART45) (ART46) (ART47) 09/113,055 09/113,057 09/113,054 09/112,752(ART53) (ART50) (ART51) (ART52) 09/112,759 09/112,757 09/112,75809/113,107 (ART58) (ART54) (ARTS6) (ART57) 09/112,829 09/112,79209/112,791 09/112,790 (ART62) (ART59) (ART60) (ART61) 09/112,78909/112,788 09/112,795 09/112,749 (ART66) (ART63) (ART64) (ART65)09/112,784 09/112,783 09/112,781 09/113,052 (DOT02) (ART68) (ART69)(DOT01) 09/112,834 09/113,103 09/113,101 09/112,751 (IJ01) (Fluid01)(Fluid02) (Fluid03) 09/112,787 09/112,802 09/112,803 (IJ04) 09/113,097(IJ05) (IJ02) (IJ03) 09/113,099 09/113,084 09/113,066 (IJ08) 09/112,778(IJ09) (IJ06) (IJ07) 09/112,779 09/113,077 09/113,061 (IJ12) 09/112,818(IJ13) (IJ10) (IJ11) 09/112,816 09/112,772 09/112,819 (IJ16) 09/112,815(IJ17) (IJ14) (IJ15) 09/113,096 09/113,068 09/113,095 (IJ20) 09/112,808(IJ21) (IJ18) (1J19) 09/112,809 09/112,780 09/113,083 (IJ24) 09/113,121(IJ25) (IJ22) (IJ23) 09/113,122 09/112,793 09/112,794 (IJ28) 09/113,128(IJ29) (IJ26) (IJ27) 09/113,127 09/112,756 09/112,755 (IJ32) 09/112,754(IJ33) (IJ30) (IJ31) 09/112,811 09/112,812 09/112,813 (IJ36) 09/112,814(IJ37) (IJ34) (IJ35) 09/112,764 09/112,765 09/112,767 (IJ40) 09/112,768(IJ41) (IJ38) (IJ39) 09/112,807 09/112,806 09/112,820 (IJ44) 09/112,821(IJ45) (IJ42) (IJ43) 09/112,822 09/112,825 09/112,826 (IJM03) 09/112,827(IJM04) (IJM01) (1JM02) 09/112,828 09/113,111 09/113,108 (IJM07)09/113,109 (IJM08) (IJM05) (IJM06) 09/113,123 09/113,114 09/113,115(IJM11) 09/113,129 (1JM12) (IJM09) (IJM10) 09/113,124 09/113,12509/113,126(IJM15) 09/113,119 (IJM16) (IJM13) (IJM14) 09/113,12009/113,221 09/113,116 (IJM19) 09/113,118 (IJM20) (IJM17) (IJMI8)09/113,117 09/113,113 09/113,130 (IJM23) 09/113,110 (IJM24) (IJM21)(IJM22) 09/113,112 09/113,087 09/113,074 (IJM27) 09/113,089 (IJM28)(IJM25) (IJM26) 09/113,088 09/112,771 09/112,769 (IJM31) 09/112,770(IJM32) (IJM29) (IJM30) 09/112,817 09/113,076 09/112,798 (IJM35)09/112,801 (IJM36) (IJM33) (IJM34) 09/112,800 09/112,799 09/113,098(IJM39) 99/112,833 (IJM40) (IJM37) (IJM38) 09/112,832 09/112,83109/112,830 (IJM43) 09/112,836 (IJM44) (IJM41) (IJM42) 09/112,83509/113,102 09/113,106 (IR02) 09/113,105 (IR04) (JM45) (IR01) 09/113,10409/112,810 09/112,766 (IR10) 09/113,085 (IR12) (IR05) (IR06) 09/113,08609/113,094 09/112,760 (IR16) 09/112,773 (IR17) (IR13) (IR14) 09/112,77409/112,775 09/112,745 (IR20) 09/113,092 (R21) (IR18) (IR19) 09/113,10009/113,093 09/113,062 09/113,064 (MEMS02) (MEMS03) (MEMS04) (MEMS05)09/113,082 09/113,081 09/113,080 09/113,079 (MEMS06) (MEMS07) (MEMS09)(MEMS10) 09/113,065 09/113,078 09/113,075 (MEMS11) (MEMS12) (MEMS13).

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

FIELD OF THE INVENTION

The present invention relates to tamper proof integrated circuitdevices.

BACKGROUND OF THE INVENTION

There is a fluctuation in current whenever an integrated circuitregister change state. If there is a high enough signal to noise ratio,it is possible for an attacker of a tamper proof security system tomonitor the difference in a standard I_(dd) current line that may occurwhen programming over either a high or a low bit. The change in I_(dd)can reveal information about keys or data. This is obviouslyundesirable.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a system resistantto attack by means of monitoring fluctuations in current lines.

In accordance with a first aspect of the present invention there isprovided a method of providing for resistance to attack of an integratedcircuit by means of monitoring current changes in a current signal inthe integrated circuit, said method comprising the step of including aspurious noise generation circuit as part of said integrated circuit foremitting electromagnetic noise and reducing Signal to Noise Ratio toobscure information in the current signal that is meaningful for theattack.

The noise generation circuit can comprises a random number generatorsuch as a LFSR (Linear Feedback Shift Register).

BRIEF DESCRIPTION OF THE DRAWING

Notwithstanding any ether forms which may fall within the scope of thepresent invention, preferred forms of the invention will now bedescribed, by way of example only, with reference to the accompanyingdrawing which illustrates a Linear Feedback Shift Register suitable foruse with the preferred embodiment.

DESCRIPTION OF PREFERRED AND OTHER EMBODIMENTS

In the preferred embodiment, a LFSR (Linear Feedback Shift Register) isutilized as a noise generator for the purpose of obscuring the I_(dd)fluctuations in a chip. The noise generator can be incorporated on anychip that manipulates secure data. This includes Smart Cards,Authentication chips, electronic keys, and cryptographic equipment. Itcan also be used as a source of pseudo-random bits for other TamperPrevention and Detection circuitry. The method of protecting againstI_(dd) fluctuation attacks is to decrease the SNR (Signal to NoiseRatio) in the I_(dd) signal. This is accomplished by increasing theamount of circuit noise and decreasing the amount of signal. The NoiseGenerator circuit described here will cause enough state changes eachcycle to obscure any meaningful information in the I_(dd) signal.

The Noise Generator circuit generates continuous circuit noise whichinterferes with other electromagnetic emissions from the chip's regularactivities and adds noise to the I_(dd) signal. Placement of the noisegenerator is not an issue on the chip due to the length of the emissionwavelengths. In a first embodiment the Noise Generator circuit cancomprise a maximal period LFSR, where the number of bits in the LFSR iscomparable to other state changes in the chip that must be protected.For example, a 32-bit microprocessor can be protected by a 64-bitmaximal period LFSR seeded with a non-zero number. The clock used forthe noise generator should be running at the maximum clock rate for thechip in order to generate as much noise as possible.

Tap selection of the 64 bits for a maximal-period LFSR (i.e. the LFSRwill cycle through all 2⁶⁴−1 states, 0 is not a valid state) yields bits63, 3, 2, 1, and 0, as shown in the drawing. The LFSR is sparse, in thatnot many bits are used for feedback (only 5 out of 160 bits are used). Asuitable LFSR design is shown in the drawing.

It would be appreciated by a person skilled in the art that numerousvariations and/or modifications may be made to the present invention asshown in the specific embodiment without departing from the spirit orscope of the invention as broadly described. The present embodiment is,therefore, to be considered in all respects to be illustrative and notrestrictive.

The present invention has been developed for utilization in an Artcamdevice.

We claim:
 1. A method of providing for resistance to attack of anintegrated circuit by means of monitoring current changes in a currentsignal in the integrated circuit, said method comprising the step ofincluding as part of said integrated circuit a spurious electromagneticnoise generation circuit for emitting electromagnetic noise and reducinga Signal to Noise Ratio to obscure information in the current signalthat is meaningful for the attack.
 2. A method as claimed in claim 1wherein said noise generation circuit comprises a random numbergenerator.
 3. A method as claimed in claim 2 wherein said random numbergenerator comprises a LFSR (Linear Feedback Shift Register).
 4. A methodas claimed in claim 3 further including the step of clocking said LFSRat a maximum clock rate of the integrated circuit.
 5. An integratedcircuit resistant to attack by monitoring current changes in a currentsignal in the integrated circuit the integrated circuit including aspurious electromagnetic noise generation circuit for emittingelectromagnetic noise and decreasing a Signal to Noise Ratio to obscureinformation in the current signal that is meaningful for the attack. 6.An integrated circuit as claimed in claim 5 wherein said noisegeneration circuit comprises a random number generator.
 7. An integratedcircuit as claimed in claim 6 wherein said random number generatorcomprises a LFSR (Linear Feedback Shift Register).
 8. A method asclaimed in claim 3 wherein a number of bits in the LFSR is comparable toother state changes in the integrated circuit that are to be protectedfrom the attack.
 9. An integrated circuit as claimed in claim 7 whereina number of bits in the LFSR is comparable to other state changes in theintegrated circuit that are to be protected from the attack.